A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design.
Chip designers often use electronic design automation (EDA) software tools to assist in the design process. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog or VHDL for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity.
Conventionally, routing is accomplished using area-based routing techniques, which is a rigid two-staged process of first performing global routing on an area followed by detail routing upon that same area. A global router does not normally make any specific connections, but provides a general plan for making the connections. During detail routing, the detailed router determines the exact location and layers for each interconnect, based upon the set of metal rules that have been provided to the chip designer.
One problem with conventional routers that use the two-stage global route/detail route approach is that there is a distinctive separation between the global router and the detail router which prevents effective and efficient interaction between the two types of routers. Another problem with conventional routers is that only two levels of granularity are available for routing, i.e., the granularity of global routes and detail routes, which may be too detailed or too coarse for certain types of desired routing activities.
To address these and other problems of conventional routers, embodiments of the present invention provide an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes.
According to some embodiments, different types of representation or levels of abstraction for the routing can be used for the same net or route. According to a particular embodiment, the different levels of abstraction includes guide representation, global segment representation, global via representation, detail segment representation, and detail via representation. In an embodiment, the levels of abstraction includes imaged geometry representation. In another embodiment, the levels of abstraction includes electrical characteristics representation.
According to some embodiments, partial topological reconfiguration, refinement, or rip-up for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. The portion that is reconfigured may correspond to any granularity of size of the route or net.
According to some embodiments, non-uniform levels of routing activities or resources may be applied to route the design. In one embodiment, prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design. This may be used, for example, to obtain fast analysis of timing for the routed design.
According to some embodiments, imaged geometry may be used to implement routing of an integrated circuit design. According to some embodiments, electrical representation may be used to implement routing of an integrated circuit design.
Some embodiments are directed to parallel processing of different portions of design.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.